1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device and also to a semiconductor device. More particularly, the invention relates to a method for manufacturing a semiconductor device having a damascene structure wherein a self-formed barrier film is provided between a wiring or via and an interlayer insulating film and also to such a semiconductor device.
2. Description of the Related Art
In copper (Cu) wiring formation process of a semiconductor device, it is general to use a damascene method wherein a wiring pattern is formed by burying a wiring groove formed in an interlayer insulating film. For the formation of Cu wiring according to the damascene method, a barrier film made of tantalum, tantalum nitride (TaN) or the like is formed in a thickness of about 10 nm, prior to the burying of Cu, so as to prevent Cu from being diffused into the interlayer insulating film. Thereafter, a Cu layer is buried in the wiring groove provided therein with a barrier layer according to an electrolytic plating technique.
However, for the reasons that as wiring pitches become finer, a level of difficulty involved in burying of Cu increases and a ratio of the barrier film to a total volume of wirings increases, resulting in a rise of wiring resistance, there has been proposed a following technique. The technique wherein a seed layer made of a Mn-containing Cu layer is formed without formation of a barrier film, followed by thermal treatment to diffuse Mn thereby forming, between the interlayer insulating film and the Cu wiring, a self-formed barrier film made of a Mn compound having a thickness of about 2 to 3 nm has been proposed. (See, for example, Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology using Self-formed MnSixoy Barrier Layer, “IEEE International Interconnect Technology Conference in 2005”, pp. 188 to 190).
The self-formed barrier process is illustrated with reference to FIGS. 7A to 7C. As shown in FIG. 7A, an interlayer insulating film 12 made of silicon oxide (SiO2) is formed on a substrate formed of a silicon wafer, after which a contact hole 13 arriving at the substrate 11 is formed in the interlayer insulating film 12, followed by burying a via 14 made, for example, of tungsten (W) in the contact hole 13.
Next, an interlayer insulating film 15 made of SiO2 is formed over the interlayer insulating film 12 including the via 14. Subsequently, a wiring groove 16 arriving at the interlayer insulating film 12 and the via 14 is formed in the interlayer insulating film 15, followed by formation of an alloy layer 17 made of CuMn over the interlayer insulating film 15 so that inner walls of the wiring groove 16 are covered therewith. This alloy layer 17 functions as a seed layer in a subsequent electrolytic plating method.
Next, as shown in FIG. 7B, a conductive layer 18 made of pure Cu is formed on the alloy layer 17 according to the electrolytic plating method in such a way that the wiring groove 16 is buried.
As shown in FIG. 7C, thermal treatment is carried out to cause Mn present in the alloy layer 17 to react with the constituent component in the interlayer insulating films 12, 15, thereby forming a self-formed barrier film 19 made of an Mn compound at the interfaces between the alloy layer 17 and the interlayer insulating films 12, 15. This self-formed barrier film 19 is formed in a thickness of 2 nm to 3 nm. At this stage, Mn is segregated at a surface side of the conductive layer 18, thereby forming a manganese oxide (MnO) layer M.
Thereafter, although not shown in the figure, the conductive layer 18 and the self-formed barrier layer 19 at portions thereof unnecessary for a wiring pattern are removed along with the MnO layer M according to a chemical mechanical polishing (CMP) method, followed by polishing down the exposed interlayer insulating film 15 at a surface side thereof to provide a wiring in the wiring groove 16.
In the wiring structure formed according to such a fabrication method as set out above, the burying characteristic of the conductive layer 18 is better over the case of a burying process using an ordinary barrier film made of Ta or TaN because of the formation of the thinned, self-formed barrier film 19 by reaction between Mn in the alloy layer 17 and the constituent component of the interlayer insulating films 12, 15. When compared with the barrier film made of Ta or TaN, the self-formed barrier film 19 is thinner, with the attendant advantage that the resulting wiring can be made low in resistance.